1. Field of the Invention
This invention relates generally to integrated circuits, and more specifically to systems and methods for generating an output oscillation signal with low jitter.
2. Description of the Background Art
As digital communications such as Synchronous Optical Network (“SONET”) and Gigabit-Ethernet strive for ever-higher data communication rates, clock generators used to synchronize data communications circuits must meet stringent stability requirements. One such stability requirement calls for low jitter. Jitter is a high frequency phase variation in the clock.
Typically, the clock generator comprises a crystal resonator to generate an oscillation signal used as a clock. Because the frequency of the oscillation signal generated in the crystal resonator is limited to about 160 MHz, frequency multiplication of the oscillation signal is typically employed to generate clock frequencies above 160 MHz. However, frequency multiplication adds phase noise and distortion, which can result in undesired jitter in the clock.
FIG. 1 illustrates a system 111 for frequency multiplication of an oscillation signal in the prior art. A buffer 101 amplifies the oscillation signal generated by the oscillator 100. Frequency multipliers 102 and 104 comprise radio frequency (“RF”) “mixers” to convert the oscillation signal to higher frequencies. Band pass filters (“BPF”) 103 reduce unwanted frequencies, and an amplifier 105 amplifies the higher frequencies. Automatic gain control (“AGC”) 108 varies a gain adjustment amplifier 109 to control amplitude of signals in the frequency multiplier 104.
One problem with the system 111 for frequency multiplication is that noise and harmonics are amplified in the mixers comprising the frequency multipliers 102 and 104. Another problem is that the gain adjustment amplifier 109 adds noise that is further amplified in the frequency multiplier 104.
One approach to reduce noise and harmonics amplified in the mixers is by summing resulting frequencies from the mixers as described in U.S. Pat. No. 5,077,546 to Carfi et al. However, this approach is relatively expensive because of the many circuit components required. Furthermore, this approach is highly frequency selective and provides relatively poor performance.
Another circuit to reduce noise and harmonics includes 90-degree quadrature mixers, as described in U.S. Pat. No. 6,456,143 to Matsumoto et al. However, 90-degree quadrature mixers comprise more active elements than zero-degree mixers, creating unwanted noise and distortion. A further problem is that this circuit is highly frequency dependent, because 90-degree quadrature mixers operate optimally over a narrow frequency range. To utilize the circuit at a different oscillation frequency requires redesigning components of the circuit.
A further approach to reducing noise and distortion amplified in the mixers is to control the amplitude of the oscillation signal. FIG. 2 illustrates a system 200 to control an amplitude of an oscillation signal in the prior art. The circuit 200 controls an amplitude of the oscillation signal at an input 210 of the frequency multiplier 240 to within a predetermined range 235. A peak detector 230 compares the input amplitude at the input 210 to the predetermined range 235. The peak detector 230 generates a control signal 250 based upon the comparison to control the amplitude of the oscillator 222. The predetermined range corresponds to a desired amplitude at the input 210 of the frequency multiplier 240, an input of the frequency multiplier 245, and/or an input 260 of the comparator 270.
The approach of FIG. 2 excites oscillation in the oscillator 222, minimizes phase noise or jitter in the oscillation signal at the input 210, and reduces the power consumed by the oscillator 222. However, one problem with the circuitry 200 of FIG. 2 is that the amplitude of the oscillation signal generated by the oscillator 222 is based upon only a predetermined range of amplitude. The amplitude of the oscillation signal is not based upon the actual amplitude of an input to a component following or “downstream” of the oscillator 222, such as the comparator 270. For example, the amplitude of the signal at the input 260 to the comparator 270 may be too high for the comparator 270 to operate optimally if the frequency multiplier 240 or the frequency multiplier 245 experience an increase in gain characteristics due to process variations, voltage fluctuations in a power supply (not shown) powering the circuitry 200, and/or a change in operating temperature of the circuitry 200.
With particular reference to clock generators for certain applications such as SONET and Fibre Channel, a very low jitter design is needed. However, prior art approaches to frequency multiplication of an oscillation signal do not give acceptable performance at low cost. Prior art oscillator designs do not provide good selectivity and low harmonic content such as is needed in a frequency multiplier approach.
Therefore, a need exists in industry to address the aforementioned deficiencies and inadequacies.